1. Field of the Invention
The invention relates to a phase comparison circuit used in PLL (phase lock loop) circuit. In particular, the present invention relates to a phase comparison circuit which keeps the PLL circuit stable, even when an input signal pulse falls out (missing).
2. Description of the Prior Art.
The PLL circuit is used to generate a reference signal according to a signal read out from the magnetic recording apparatus, optical disc apparatus and so on to reproduce a correct read out signal synchronized with this reference signal. The PLL circuit always compares a phase of the input signal with that of the output reference signal outputted from VCO (voltage controlled oscillator), and controls the resultant output voltage of VCO to produce a reference signal synchronized with the input signal.
FIG. 7 shows a conventional PLL circuit. FIG. 8 is a timing chart of FIG. 7 showing signal wave forms at corresponding portions of PLL. Signal wave forms (b), (g), and (f) in FIG. 8 correspond to signal voltages in the PLL circuit of FIG. 7, respectively.
In FIG. 7, the numeral 100 denotes a phase comparison circuit, the numeral 200 denotes a charge pump, the numeral 300 denotes a VCO (voltage controlled oscillator) and the numeral 400 denotes a frequency divider. The phase comparison circuit compares a phase of the input data signal (a) and that of the reference signal (b) outputted from the frequency divider 400. When the phase of reference signal (b) leads that of the input signal (a), an output signal (g) is generated.
When the phase of the input signal (a) is delayed with respect to to the phase of the reference signals (b), an output signal (f) is generated. The charge pump 200, for example, increases the output voltage when output signal (g) is inputted (UP output signal) and decreases the output voltage when output signal (f) is input (DOWN output signal). VCO 300 increases the output frequency when the input voltage rises, and descends it when the input voltage descends. This output frequency is divided by the frequency divider 400 and is dropped to the frequency almost the same as that of the input data signal (a).
In other words, the PLL circuit shifts forward the reference signal (b) when the phase of the input signal (a) is more advanced than that of the reference signal (b) and delays the reference signal (b) when the phase of input signal (a) is behind that of the reference signal (b). Thus, it always operates to synchronize the reference signal with the input signal.
However, in the PLL circuit as shown in FIG. 7, the output signal (g) is controlled to become 1 at rising edge of the input signal (a) and to become zero at rising edge of the reference signal (b). Therefore, when any of the input signal pulses is missing, as shown in the hatching portion of the output signal (f), the output signal (f), which changed to 1 at rising edge of the reference signal (b), cannot become zero and then remains in the state of 1 since the succeeding input signal (a) does not appear.
As a result, the output signal (f) makes the output voltage of charge pump 200 descend and the frequency of VCO 300 decrease. In case the input signal pulse is missing, neither the output signal (g) nor (f) must be generated. However, the voltage of the output signal is applied to the charge pump 200, which makes the output frequency of the VCO fluctuate. Therefore, the stable PLL could not be supplied as a result.
To solve this problem in the conventional method, the input data signal and the reference signal are compared after a predetermined amount of time after the input data signal or the reference signal have arrived. However, this conventional method had a disadvantage in that the accuracy and stability of the circuit which generates a predetermined amount of time affects directly upon the performance of the PLL circuit.